The present invention generally relates to parity inversion test systems, and more particularly to a parity inversion test system which is used in a bus interface circuit and the like and is especially suited for a case where input/output data lines having different data widths are connected to the interface circuit.
The parity inversion test is used to test whether or not the parity check function is operating normally. In a data bus, communication channel and the like, the parity inversion test is carried out by generating a parity data by inverting arbitrary bits of an input data and making a check to determine whether or not an error is detected on the receiving end.
It is desirable to carry out the parity inversion test also when the interface circuit is connected to buses having different bus widths for the input and output. In this case, it is also desirable that the parity inversion test be carried out correctly for all data widths using an input with a minimum data width, the test time be short, and the parity inversion test be simple.
FIG. 1 shows an example of an interface circuit having different input/output data widths. This interface circuit connects a data line having a data width of 32 bits and a data line having a data width of 64 bits. The interface circuit shown in FIG. 1 includes buffers 11 and 12 respectively made up of 64-bit first-in-first-out (FIFO) buffers, a parity generating circuit 13 and a parity check circuit 14 which are connected as shown.
In FIG. 1, the data from the 32-bit data line is alternately input to the FIFO buffer 11 as the upper bits 0 to 31 and the lower bits 32 to 63. The data are read out from the FIFO buffer 11 in parallel as a 64-bit data and output via the 64-bit data line.
In addition, the data from the 64-bit data line is input in parallel to the FIFO buffer 12. The data is alternately read out from the FIFO buffer 12 as the upper bits 0 to 31 and the lower bits 32 to 63 and output via the 32-bit data line.
The parity generating circuit 13 generates a parity data with respect to the 64-bit output data of the buffer 11 at a rate of 1 bit in 8 bits. The 8-bits parity data from the parity generating circuit 13 is output via a parity line.
At the receiving end which receives the data from the 64-bit data line via a data bus or a communication line, the parity check circuit 14 generates the parity data with respect to the received 64-bit data similarly to the transmitting end, and compares the parity data with the 8-bits parity data which is received from the transmitting end via the parity line. If the two compared parity data do not match, the parity check circuit 14 generates an error detection signal which indicates an error in the data bus or the communication line.
FIG. 2 shows a bus sequence at the input side of the interface circuit shown in FIG. 1, that is, the bus sequence on the 32-bit side. FIG. 2 shows an access of an odd number of words and a 1-word access in particular, and an access of an even number of words and a 4word access in particular.
In the case of the access of an odd number of words, a data Data 1 amounting to 1 word is read in response to a clock signal when a bus start signal BS is generated. The bus start signal BS indicates the start of the access. On the other hand, in the case of the access of an even number of words, data Data 1 through Data 4 amounting to four words are read in response to each clock signal based on a block signal BK which indicates the size of the data block when the bus start signal BS is generated.
FIG. 3 shows an example of a conventional parity inversion test system. In FIG. 3, those parts which are the same as those corresponding parts in FIG. 1 are designated by the same reference numerals, and a description thereof will be omitted. As shown in FIG. 3, a 2-bit counter 15 and AND gates 16 and 17 are provided.
A data "0" is applied to an input terminal D of the counter 15. The counter 15 starts to count from "0" in response to a clock signal which is applied to a clock input terminal CP when the bus start signal BS is applied to a load input terminal L, and generates at an output terminal Q a signal which is inverted for every clock signal.
First, the AND gate 16 opens in response to the output signal "0" of the counter 15, and 1 word of data from the 32-bit data line is read into the buffer 11 as the upper bits 0 to 31. Next, the AND gate 17 opens in response to the output signal "1" of the counter 15, and 1 word of data from the 32-bit data line is read into the buffer 11 as the lower bits 32 to 63. Similarly thereafter, the data from the 32-bit data line is alternately written into the buffer 11 as the upper bits and the lower bits. Hence, when the upper and lower bits are read out from the buffer 11 in parallel, it is possible to output a 64-bit data via the 64-bit data line.
The parity generating circuit 13 generates 1 bit of parity data for every 8 bits of the 64-bit output data of the buffer 11, and outputs the 8-bits parity data to the 8-bits parity line. With respect to the input data, the parity generating circuit 13 generates the parity data by inverting codes of the bits which are specified by an external signal, so that the parity inversion test can be carried out.
FIG. 4 shows the parity generating circuit 13 shown in FIG. 1. The parity generating circuit 13 shown in FIG. 4 is made up of a parity generating part 13a and an AND gate 18.
In order to carry out the parity inversion test, the bits of the 8-bits input data the codes of which are to be inverted are specified by a parity inversion bit specifying signal. When carrying out the parity inversion test, a test mode specifying signal which specifies the test mode is input so as to generate a 1bit output from the AND gate 18. Hence, the parity generating part 13a generates the parity data with respect to the data which is obtained by inverting specified bits of the 8-bits output data of the buffer 11, and the parity data is output via the parity line.
FIG. 5 shows a state where 1 word is stored according to the conventional system. A 64-bit buffer 19 shown in FIG. 5 may be used as the buffer 11 or 12. In the case shown in FIG. 5, 1 word of data Data 1 having 32 bits is read into the upper bits 0 to 31 of the buffer 19. No data corresponding to the lower bits 32 to 63 is read into the buffer 19, and thus, the data corresponding to the lower bits 32 to 63 is undetermined as indicated by "*".
Therefore, when conventionally carrying out the parity inversion test using the construction shown in FIG. 3 at the 64-bit side of the interface circuit which connects the 32-bit data line to the 64-bit data line, for example, the data is stored in the buffer 19 as shown in FIG. 5 if a 1-word access (odd number of words) is made as shown in FIG. 2. In this state, when the data is transmitted to the 64-bit data line, the data appears in the upper bits 0 to 31, but the value of the data output to the lower bits 32 to 63 becomes undetermined. If the bits of the data output to the lower bits 32 to 63 are fixed to "0" or "1" the parity inversion test cannot be carried out in a satisfactory manner. For this reason, according to the conventional parity inversion test system, there is a problem in that a two-word data (even number of words) must be input to the upper bits and to the lower bits of the 64-bit buffer 19 from the 32-bit data line.
The above described problem is not limited to the interface circuit which connects the 32-bit data line with the 64-bit data line. In general, in an interface circuit which connects first and second data lines where the ratio of the data widths of the first and second data lines is N:nN, it is necessary to input a nN-bit data from the N-bit data line.